GPS World, August 2015

RECEIVER TECNOLOGY Signal Quality and Authentication FIGURE 3 Normalized ChipShape falling edges for the GPS SPS Constellation of June 2014 when rising edges are aligned to zero function that selects the closest ChipShape vector index that corresponds to relative code phase x Each ChipShape processing bank is configured to span one chip early and one chip late with a resolution of N bins per chip thus producing a ChipShape vector of 3N bins α is a scale factor obtained through trial and error to yield robust tracking performance as observed by the code minus phase measurement For the result shown in Figure 1 N 240 and d 0017 chips The figure clearly shows that the rising edge zero crossings vary by SV This variation is due to nominal signal deformation present in each GPS SPS signal FIGURE 2 illustrates the rising edge zero crossings aligned to zero relative code phase This alignment was performed by interpolating each R NPN vector precisely estimating code phase at the zero crossing point and shifting the curve appropriately FIGURE 3 shows zero crossings for the falling edges after all rising edges were aligned to zero The figure clearly illustrates subtle asymmetries between positive and negative chips which span a range of approximately 15 meters These asymmetries are not directly observable using typical GNSS receiver processing However they can lead to pseudorange biases through the resulting distortion that occurs to the traditional correlation function In general a family of code discriminators that precisely track chip rising edge zero crossings can be defined by 2 Where R NPX is a linear combination of orthogonal ChipShape components that preserve the rising edge transition e g R NPX R NPN R NPP R FFX is a linear FIGURE 4 Procedure for estimating scale factors and biases for rising edge tracking early late and double delta code discriminators FIGURE 5 Uncorrected rising edge early late discriminator functions for various correlator spacings combination of orthogonal ChipShape components that preserve the non transitioning that is flat sections of chips for eample R FFX R PPP R PPN R NNP R NNN a and b define an integration interval within the range 1 to 2 chips with respect to the chip transition edge β is a bias compensation term represents the real or imaginary component function for the coherent discriminator depending on the modulation phase of the signal being tracked or the magnitude function for a noncoherent discriminator implementation Similarly a family of code discriminators that precisely track chip falling edge zero crossings that occur one chip after the rising edges tracked by the discriminator of Equation 2 can be defined by 3 GPS World August 2015 www gpsworld com 40