GPS World, December 2009
Baseband CPU die 1 On Chip CPU Baseband Processor Serial Interface Real Time Processing Navigation Processing SRAM Boot ROM Flash Memory die 2 RF Tuner die 3 SOC Complete GPS Receiver in a Single Chip Package Baseband Processor Navigation Processing RF Tuner Serial Interface Serial Interface State Machine Controller Host Based GPS IC single die Host CPU Å FIGURE 3 Host based architecture compared to SOC SOCs throughout the last decade and to date looked like FIGURE 3 The host based architecture by contrast needs no CPU in the GPS Instead GPS software runs on the CPU and flash memory already present on the host device for example the smartphone Meanwhile radio frequency complementary metal oxide semi conductor RF CMOS technology allowed the RF tuner to be implemented on the same die as the baseband Host based GPS and RF CMOS together allowed us to make single die GPS chips The effect of this was that the cost of the chip went down dramatically without any loss in performance FIGURE 4 shows the relative scales of some of largest selling SOC and hostbased Receiver Design WIRELESS Serial Interface NMEA Parser SOC Host based Location Application Host CPU Location Application chips to give a comparative idea of silicon size and cost The SOC chip on the left is typically found in devices that need a CPU while the host based chip is found in devices that already have a CPU In 2005 the worlds first single die GPS receiver appeared Thanks to the single die it had a very low bill of materials BOM cost and has sold more than 50 million into major brand smartphones and feature phones on the market Review We have seen that E 911 was the big catalyst for getting GPS into phones although initially only in CDMA and iDEN phones E 911 became the driv Å FIGURE 4 Relative sizes of host based compared to SOC www gpsworld com December 2009 GPS World 39
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