GPS World, January 2018

The Continued Evolution of the GNSS Software Defined Radio BY James T Curran Carles Fernández Prades Aiden Morrison and Michele Bavaro SoC GPP FPGA d GPP Cloud processing RFSoM RFSoC GPP FPGA e f GPP Front end JANUARY 2018 WWW GPSWORLD COM GPS WORLD 43 WITH RICHARD B LANGLEY GETTING BETTER ALL THE TIME T he software defined radio SDR has an infinite number of interpretations depending on the context for which it is designed and used By way of a starting definition we choose to use that of a reconfigurable radio system whose characteristics are partially or fully defined via software or firmware In various forms the SDR has permeated a wide range of user groups from military and business to academia and the hobby radio community SDR technology has evolved steadily over the decades following its birth in the mid 1980s with various surges of activity being generally aligned with new developments in related technologies processor power serial busses signal processing techniques and SDR chipsets At present it appears that we are experiencing one such surge and the GNSS SDR is expanding in many directions The proliferation of collaboration and code sharing sites such as GitHub has enabled communities to share and co develop receiver technology the rise in the maker culture and crowdsourcing has led to the availability of high performance radio frequency RF front ends and the adoption of SDRs by some major telecommunications companies has led to the availability of suitable integrated circuits These contributing factors have played a part in an increased uptake of GNSS SDRs in military scientific and commercial applications In this article we explore the recent trends and the technology behind them SDR TOPOLOGIES The software defined radio for GNSS has evolved over the past decade both in terms of the adoption of new frequencies new signals and new systems as they have become available as well as the adoption of new processing platforms and their associated processing techniques Shown in FIGURE 1 is a simplified depiction of how the topology of the softwaredefined GNSS receiver has evolved over the years a d with a hint at where it might go next e f In a traditional GNSS SDR as depicted in Figure 1 a the RF front end typically interfaces with the general purpose processor GPP through a standard bus and intermediatefrequency IF samples are streamed to a buffer Once on the GPP basic operations such as correlation acquisition tracking measurement generation and positioning were performed Of all of the operations performed by a GNSS receiver correlation is by some orders of magnitude the most computationally intensive However the correlation operations are relatively simple often requiring only integer arithmetic and can be easily parallelized When running on modern processors optimized software receivers can avail themselves of multi threading task parallelism or the operations can be vectorized to exploit data parallelism single instruction multiple data Beyond a certain number of GNSS signals and a certain bandwidth a GPP simply cannot cope and many SDR receivers looked to hardware acceleration for the correlation process This either took the form of a graphics processing unit GPU or a field programmable gate array FPGA as depicted in Figure 1 b both of which are well suited to highly parallel tasks These processing platforms can be powerful and efficient and so can almost alleviate all challenges associated with correlation This is not the only way to alleviate the processing burden as it is also possible to delegate the correlation task to a network of computers This cloud receiver architecture depicted in Figure 1 e has received particular attention of late showing promise for certain niche applications This computation in the cloud trend has partially reverted with the proliferation of many core desktop and mobile processors but at a certain level of signal or processing complexity the extensions remain applicable Nowadays data throughput becomes an important a GPP GPU or FPGA b GPP FPGA c Front end Front end Front end Front end Front end FIGURE 1 A simplified depiction of different SDR topologies GPP generalpurpose processor GPU graphics processing unit FPGA field programmable gate array SoC system on chip RFSoM radio frequency system on module RFSoC radio frequency system on chip