GPS World, January 2018

10000 1000 100 USB 31 USB 30 Ethernet gigabit USB 20 PCIe 30 x8 PCIe 20 x8 PCIe 10 x8 Instruction a fully integrated system this connection still exists but it is typically a trace on a circuit board or even a pathway within an integrated device In contrast in an SDR this often takes the form of a cable or connector between the physically discrete system modules In cases where the devices are discrete it is often necessary to implement some data buffering on both ends of the bus The suitability of a particular bus is often determined by the sustained data throughput rate required by the application and in some cases the latency of the bus An example of a number of interfaces popular in modern SDR front ends is shown in FIGURE 2 illustrating the nominal throughput and the minimum latency of each In the case of a GNSS SDR the minimum conceivable throughput required would be hundreds of megabytes per second but a system could easily use in excess of 200 megabytes per second for multifrequency high bit depth data Of course in post processing applications bus latency is not a factor However certain 46 GPS WORLD WWW GPSWORLD COM JANUARY 2018 applications may require that this latency is small or bounded or somehow deterministic Applications such as closed loop vehicle control or certain safety systems might impose tight requirements on latency High or unpredictable latency in GNSS measurements might lead to loop instability in the case of a control system or might erode safety margins Although the trend in modern interfaces is for higher throughput only certain interfaces offer low latency The Silicon In comparison with less flexible fixed function GNSS receiver chips GNSS SDR hardware platforms provide the opportunity to exchange one to three orders of magnitude of power consumption and system size to gain substantial control over the characteristics of the design Moreover one of the other main differences between GNSS front ends and general purpose SDR front ends is the number of bits of ADC resolution and the conversion linearity Both contribute to power consumption However it may be worth considering that GNSS specific front ends have not received as much attention as telecommunications front ends and consequently there is at least a generational gap in silicon mask technology most GNSS products are at the 350 nanometer level In terms of GNSS specific devices products such as the SiGe SE4110L the Maxim MAX2769 and Saphyrions SM1027U provide a solution for slightly flexible L1 GPS Galileo or in some chip revisions GLONASS operation These kinds of chips support a few sampling rates and filtering configurations In the middle ground are the much more flexible chips from Maxim including the MAX2120 and MAX2112 which provide total L band coverage a myriad of filtering options and adjustable gain control all within a 03 watt power budget per channel RF portion only These chips allow for singleband coverage of adjacent GNSS signals such as GPS and GLONASS L1 or L2 in a single non aliased RF band In terms of multi channel options devices such as the Maxim MAX19994A or the NTLab NT1065 offer dual or quad channel functionality respectively Similar functionality can be achieved by pairing downconversion and IF receiver ICs such as for example the Linear Technologies LTC5569 dual active downconverting mixer and the Analog Devices AD6655 IF receiver which might offer sufficient performance for high accuracy dual frequency positioning Higher up the cost power and complexity structure are radios designed explicitly to support SDR applications that happen to cover GNSS bands such as the Lime LMS6002d LMS7002M and the Analog Devices AD9364 Notably these provide receive and transmit channels and frequency coverage up to 6 GHz Another interesting and relevant trend is in the use of direct RF sampling ICs which offer the possibility of full L band coverage and multi antenna support Examples include the 01 1 10 100 1000 10 Ethernet fast PCI Latency microseconds Bandwidth megabytes per second FIGURE 2 Bandwidth vs latency scatter plot for popular buses PU PU PU PU PU PU PU PU Results Arguments FIGURE 3 Illustration of the operation of single instruction multiple data SIMD processors which take a multiple data input arguments and produce multiple results given a single instruction operated in parallel in a set of processing units PUs